Description
SpyGlass Lint
Early Design Analysis for Logic Designers
Inefficiencies during RTL design usually surface as critical design bugs during the late stages of design implementation. If detected, these bugs will often lead to iterations, and if left undetected, they will lead to silicon re-spins. The SpyGlass® product family is the industry standard for early design analysis with the most in-depth analysis at the RTL design phase. SpyGlass provides an integrated solution for analysis, debug and fixing with a comprehensive set of capabilities for structural and electrical issues all tied to the RTL description of design.
Introduction
With soaring complexity and size of chips, achieving predictable design closure has become a challenge. A multitude of coding style, structural and electrical design issues can manifest themselves as design bugs and result in design iterations, or worst still—silicon re-spins. Other tools may detect design bugs but often at late stages of design implementation, after a significant investment in time and effort has already been made. As design teams become geographically dispersed, consistency and correctness of design intent becomes a key challenge for chip integration teams. Emphasis on design reuse and IP integration requires that design elements be integrated and meet guidelines for correctness and consistency.
Features and Benefits
- Sophisticated static and dynamic analysis identifies critical design issues at RTL
- A comprehensive set of electrical rules check to ensure netlist integrity
- Includes design reuse compliance checks, such as STARC™ and OpenMORE to enforce a consistent style throughout the design
- Customizable framework to capture and automate company expertise
- Integrated debug environment enables easy cross-probing among violation reports, schematic and RTL source
- The most comprehensive knowledge base of design expertise and industry best practices
- Supports Verilog, VHDL, V2K, SystemVerilog and mixed-language designs
- Tcl shell for efficient rule execution and design query
- SoC abstraction flow for faster performance and low noise
SpyGlass CDC
Comprehensive, Low-Noise Clock Domain Crossing Verification
Among the many verification challenges confronting system-on-chip (SoC) designers today, clock domain crossings (CDC) ranks near the top in difficulty. Today’s SoCs have dozens or sometimes even hundreds of asynchronous clock domains, making it very difficult to verify using conventional simulation or static timing analysis (STA). RTL simulation is not designed to verify metastability effects which cause data transfer issues across asynchronous clock boundaries and STA does not address asynchronous clock domains issues.
Introduction
CDC issues have become a leading cause of design errors. Such errors can add significant time and expense to the design-and-debug cycle, and may even find their way into silicon, necessitating costly respins. Besides the traditional CDC issues, Reset Domain Crossing (RDC) issues can also cause metastability in signals. Use of asynchronous resets is becoming more prevalent because of the wider use of multiphase power-up/boot sequences, etc. As a consequence, RDC issues are causing more and more design errors. (Please refer to the SpyGlass RDC Datasheet for more information about these reset domain crossing capabilities.) For both of these types of issues, SpyGlass® provides a high-powered, comprehensive solution.
Contact email for obtaining software installation package: gosoftvip@163.com The resources are sourced from the internet, and this introduction is for learning purposes. If there is any infringement, please contact us for deletion!
For more info write me
Email : gosoftvip@163.com
telegram : @sacyou888